Vacancy caducado!
- Design architecting and trade-off analysis
- RTL coding and verification
- Controller + PHY integration and verification
- FPGA targeting
- Customer delivery and support
- Strong Verilog RTL design and verification expertise
- Questa/Incisive/VCS simulator experience
- Python/Perl/Tcl scripting experience
- Significant ASIC and/or FPGA design experience
- Ability to learn quickly and work independently
- Solid communication and project management skills
- 5+ years of logic design experience
- ASIC synthesis, timing constraint, CDC/RDC experience
- Memory (HBM/DDR/LPDDR), PCI Express, or MIPI expertise
- Located in the Portland, Oregon area
Vacancy caducado!