Vacancy caducado!
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, Silicon Manufacturing and Package Engineering team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.We are looking for a Senior Analog Design Engineer to join the team.Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.Responsibilities
Responsible to design and integratethe analog building blocks into bigger systems for example: ADC, DAC, LDO, PLL, Temperature Sensors, DC-DC converters.
Use industry EDA tools (Cadence, Mentor, or Synopsys) for schematic capture and simulation setup to analyze and perform pre and post-layout simulations of the analog basic building blocks across PVT.
Design, model, and simulate Power Delivery Solutions (i.e., incl. IP design, voltage regulator, motherboard, CPU package, silicon, and decoupling capacitor solution) for data center processors and corresponding platforms to ensure optimized performance.
Support the Mixed Signal Design Engineer with top level simulations to ensure the correct integration of analog, digital and software components.
Collaborate with Test Engineers to develop test plans and ensure that the design can be efficiently and fully tested in production.
Participate in design reviews and create the necessary design and product documentation.
Supervise IC layouts to achieve the optimal design performance and power.
Support Root Cause and Failure Analysis investigations.
Work with multi-disciplinary and international project team members.
Embody our Culture (https://www.microsoft.com/en-us/about/corporate-values) and Values (https://careers.microsoft.com/us/en/culture)QualificationsRequired Qualifications: 7+ years of related technical engineering experienceo OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experienceo OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experienceo OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
4+ years of experience in a role that involves mixed-signal design.
3+ years of experience working with large cross-functional teams with diverse opinions.
Other Requirements:Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings:Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. Preferred Qualifications:
Demonstrated experience in design through volume production of modern SOCs
Experience with Foundry Silicon and packaging technologies.
Proficient with the latest mixed-signal design flows and tools.
Experience with Power Delivery or Power Management Circuits
Experience with Design Flow automation and scripting.
Analyze and drive characterization and test data from lab and high-volume testing.
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $117,200 - $229,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $153,600 - $250,200 per year.Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-payMicrosoft will accept applications for the role until August 12, 2024.Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .
Vacancy caducado!