Vacancy caducado!
The Role: The Display Controller team within the Radeon Technologies Group(RTG) is looking for an individual to participate in the Display IP deployment into various SOCs. Key Responsibilities: Understand the functional and performance requirements of the Display IP within an APU and dGPU SOC Scope requirements and resources to meet project schedules Compose test and coverage plan to ensure functional completeness in a SOC environment Work with SOC teams to debug test environment issues and failing test cases. Provide hands-on leadership of a small team of Engineers as required to meet program development goals Provide mentorship and/or act as a liaison between IP and SOC design teams for synthesis and physical layout issues Codeline management Signoff IP quality for delivery into SOC Optimally connect with multi-disciplined teams located across the globe Capture, attend, and present technical status on a weekly basis Preferred Experience: Minimum 7+ years of ASIC design work experience Have in-depth knowledge of the entire design implementation process from micro-architecture, design specification, RTL design and functional verification, synthesis, timing, and formal verification Proficiency with Verilog or System Verilog Experience with multi-clock domain designs Experience in IP development and delivery Design knowledge of data processing, digital filters, encoder/decoders, arbitration algorithms, protocol designs, and display related standards Strong problem-solving skills Demonstrates the ability to be coached and capable of mentoring others Strong written and verbal communication to engage with team members and other customers Academic Credentials: Min. Bachelor of Science Degree in Electrical Engineering, Computer Science, or Computer Engineering
Vacancy caducado!