Vacancy caducado!
We are looking for a NoC Architect who will work with a world-class group of researchers and engineers. This ideal candidate will understand the full spectrum of design choices when tackling the data flow aspects of heterogeneous SoC integration, from optimizing throughput and QoS to shared memory while minimizing energy, through structuring routing topologies to assure timing closure for NoCs that span voltage, power and clock domains. Beyond connectivity, the candidate will contribute to the specification and deployment of advanced features in distributed cache coherence, memory management, security enforcement and error control.Successful candidates for this role will also have an excellent grasp on SoC architecture and the performance characteristics of heterogeneous processing subsystems, experience with a variety of on-chip interface protocols, comfortable in operating in a cross-functional environment, and a hands-on approach to problem-solving.
- Microarchitecture definition and implementation of NoC fabrics for a chip subsystem or entire SoC
- Architecture definition and specification of feature improvements for a NoC generator
- Work across architecture, micro-architecture, design, physical implementation, prototyping, performance analysis/optimization, and testing for multiple projects
- Work cross-functionally with SoC architecture, Modeling, FW, prototyping and development teams
- Works effectively as an individual and in a multidisciplinary international team
- MS EE/CS or equivalent experience
- 2+ years of experience integrating SoCs or complex IP-based subsystems as a Silicon Architect, Digital Design Engineer, or NoC Architect
- Experience in evaluating trade-offs such as speed, performance, power, area
- Experience in employing scientific methods to debug, diagnose and drive the resolution of cross-disciplinary design issues
- Hands-on experience in digital design, logic simulation and performance analysis
- Understanding of on-chip interface protocols such as AMBA AXI or OCP
- Understanding of DRAM performance optimization
- Experience with scripting languages like Python to facilitate task automation
- Experience in SystemC/TLM2 performance modeling
- Experience implementing multiprocessor cache coherence and memory management
- Experience implementing end-to-end Quality of Service for heterogeneous processing systems
- Experience with performance and power modeling of chip subsystems
- Experience collaborating and/or leading in a team environment
Vacancy caducado!