Design for Test Engineer (m/f/d) - REF84987L

As DFT engineer (m/f/diverse) for Continental ASICs you define and implement DFT (Design for Test) and BIST (Built-In Self-Test) concepts, you also develop DFT specifications and driving DFT architecture and methods for designs as well as IPs to maximize test coverage while minimizing costs.You have the opportunity to work on Continental’s diverse innovative automotive applications and find optimized solutions for their specific needs. Special care must be taken to meet the stringent automotive requirements.Your tasks will focus on the following activities:Define and implement DFT (Design for Test) and BIST (Built-In Self-Test) concepts, as well as IPs to maximize test coverage while minimizing costsDefine and develop scripts for automatic scan insertion, execute scan insertion and ATPG (Automatic Test Pattern Generation)Perform test coverage analysis and improvementLead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plansDevelop full chip and block level DFT implementation from the Specifications and product coverage, quality, and manufacturability goalsCollaboratively create DFT methodology innovations & enhancements for ContinentalWork in close cooperation with the two main interfaces chip design and semiconductor manufacturing as well as related areasImplement and verify testability features to our System-on-Chip designsCreate and simulate test patterns for production testingDevelop DFT specifications and drive flow and methodology enhancementsImplement and validate DFT structures such as LBIST, MBIST, IP tests, Scan & compression etc.Give technical guidance to other DFT engineers, concept engineers, digital designers, physical implementation, and functional verification teamsVerify, support and understanding of pattern delivery to the post-silicon test engineering teams. Delivering the full chip requirements for the Test Engineering Team. Understanding tester requirements and delivering the patterns in the formats that the tester team’s needsWork with cross-functional IP and SOC teams to define strategy for DFT architecture, verification, and design flow automationContribute throughout the whole development and give early feedback to the Concept, Architecture and Design Teams for possible issues for DFTDefine, develop, improve DFT process flows and methodologies for continuous improvementWorking closely with IC Design during test plan and DFT definition, pre-silicon verification (chip level verification) and post silicon validationWork closely with IP test development team, defining test schemes and implementation styles