FPGA Verification and Validation Senior Engineer

In this role you will: Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program Run formal verification of complex blocks to ensure functional correctness Implement a verification environment to facilitate testing of the RTL against reference MATLAB/C models Provide verification support to Design Engineering teams by simulating, analyzing, and debugging block-level design and integrated system Qualities of a successful candidate: MS in Electrical Engineering, Computer Engineering or equivalent 3+ years of experience in verification, preferably in communication systems Knowledge of SystemVerilog, UVM principles, bash/shell scripting, MATLAB, and Git Experience with Questasim