Vacancy caducado!
- Overall, responsible for verification of ASIC designs To include such things as:
- Design Verification – Implement test benches in UVM and Sytem Verilog, run regressions at RTL and gate level, generate and report DV metrics with respect to bug tracking and code coverage, debug failures and provide feedback to the design
- Have experience with UVM
- Have a full chip verification experience
- Knowledge of industry standard interfaces. Familiarity with Verilog, Simulation tools & ability to debug Problems & Troubleshoot
- Knowledge of ASIC design and verification flow including RTL design, simulation, test bench development, regression, equivalence checking, timing analysis, scan insertion and test pattern generation
- Functional understanding of constrained random verification process, functional coverage, and code
Vacancy caducado!