Vacancy caducado!
- Experience with high performance digital blocks for mixed signal ICs.
- Proficient with Verilog-HDL & System Verilog coding.
- Understanding of high speed DSP applications, clock domain crossing will be helpful.
- Understanding & exposure to verilog AMS simulation, experience in behavioral models of analog circuit will be plus.
- Proficient with Cadence tools such as NCVerilog, NCSIM, Simvision. Experience with linting tools (i.e Spyglass) will be helpful.
- Exposure to SDF annotated simulations with good understanding of parasitic delays and timings is required.
- Independent, self-motivated with good analytical & communication skills.
Vacancy caducado!