Job DescriptionWe are looking for an experienced Verification Engineer with a focus on FPGA design to join our growing team in San Jose. The ideal candidate will have a strong background in Verilog, UVM (Universal Verification Methodology), and experience with digital design, lab skills, and debugging. You will work on current Cisco routers, contributing to the development of new chassis and design work. This is a critical role for immediate large-scale projects, where design verification quality has been a key challenge.Key Responsibilities:Develop and modify System verilog test cases for digital design verification.Perform FPGA design tasks, including Verilog coding, simulations, and lab debugging.Collaborate with the design team on-site 5 days a week, ensuring smooth execution of verification plans.Work closely with networking technologies (e.g., Cisco) and participate in verification efforts.Coordinate with engineers to meet project deadlines for chassis and route design.Provide expertise in verification for FPGA and design environments, addressing challenges in finding qualified talent.Requirements:10+ years of experience in FPGA design, Verilog, and verification processes.Strong background in UVM and simulation methodologies.Proven experience with digital design, lab skills, and debugging in FPGA environments.Ability to work on-site in San Jose 5 days a week and collaborate effectively within a team.Experience in networking systems (e.g., Cisco) is a plus.We are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal opportunity/affirmative action employer that believes everyone matters. Qualified candidates will receive consideration for employment regardless of their race, color, ethnicity, religion, sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military or uniformed service member status, or any other status or characteristic protected by applicable laws, regulations, and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or recruiting process, please send a request to [email protected] . To learn more about how we collect, keep, and process your private information, please review Insight Global's Workforce Privacy Policy: https://insightglobal.com/workforce-privacy-policy/ .Skills and RequirementsUVMVerilogSystemsVerilogVerification FPGA nullWe are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal employment opportunity/affirmative action employer that believes everyone matters. Qualified candidates will receive consideration for employment without regard to race, color, ethnicity, religion,sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military oruniformed service member status, or any other status or characteristic protected by applicable laws, regulations, andordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request to [email protected].
Job Details
ID | #52674636 |
Estado | California |
Ciudad | Sanjose |
Full-time | |
Salario | USD TBD TBD |
Fuente | Insight Global |
Showed | 2024-10-10 |
Fecha | 2024-10-10 |
Fecha tope | 2024-12-08 |
Categoría | Etcétera |
Crear un currículum vítae | |
Aplica ya |
Verification Engineer
California, Sanjose, 95101 Sanjose USA