Vacancy caducado!
- Collaboration with offshore team.
- IC role and offshore task coordination
- Must have 10+ yr experience with ASIC design activities – Verilog RTL, testcase debug, netlist checks, CDC checks, coverage analysis, timing closure, x-prop/gate level simulations.
- Domain knowledge in PCIE/CXL, DDR, AMBA AXI/APB protocols.Please note: We strongly prefer the ASIC experience. If FPGA-only experience, then domain knowledge is must.
Vacancy caducado!