Vacancy caducado!
Reference #: R1086-24
Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc.People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our ; we affectionately refer to it as the Aggregate System and it's won us countless awards for diversity and workplace excellence.Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over without a great team dedicated to empowering innovation. People like you.Visit our page to see what exciting opportunities and company await!Job Description:As a principal Layout Designer, the candidate will work closely with Microchip's Engineering Services team to complete analog layout tasks of integrated circuits for world-wide design teams. As a principal level candidate, he/she will:
Continue to master the art of analog layout of CMOS and FinFet integrated circuits
Learn various different technology nodes and tool methodologies to serve varying BU needs
Train new college graduates in analog layout methodologies over multiple technology nodes
Demonstrate expertise in the Cadence IC Layout tools and Siemens Calibre PDV tools
Analyze and debug results of PDV tools for LVS, DRC, LPE, ERC, & EM/IR.
Complete cell layouts of varying complexity while mentoring junior layout engineers
Utilize design collaboration tools with local and world-wide teams
Work on a computer workstation in the Linux OS environmentRequirements/Qualifications:Bachelor's degree, or, Associate's degree with >8.5 yrs. experience, majoring in Electronic Engineering, Electronic Engineering Technology or related program
Firm understanding of analog layout principles in CMOS and/or Finfet technologies
Expertise with Cadence IC layout tools
Expertise with industry standard physical verification tools in Mentor, Cadence, & Synopsys
Firm understanding of the impact of good layout techniques on wafer yield
Ability and desire to train junior team members in analog layout
Excellent organizational skills and detail oriented
Effective communication skills, strong work ethic, and the desire to continually learn
Microsoft Office skills with focus in PowerPoint, Excel, and WordTravel Time:
0% - 25%Physical Attributes:
Hearing, Seeing, Talking, Works Alone, Works Around OthersPhysical Requirements:
80% Sitting, 10% Walking, 10% StandingMicrochip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.For more information on applicable equal employment regulations, please refer to the and the . Please also refer to the .Microchip is an Equal Opportunity/Affirmative Action Employer of Disabled/Veterans/Minorities/Women. We provide equal employment and affirmative action opportunities to applicants and employees without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, protected vetera status, disability, or any other basis protected under applicable federal, state or local laws.