Vacancy caducado!
Facebook Reality Labs (FRL) focuses on delivering Facebook's vision through Virtual Reality (VR) and Augmented Reality (AR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom silicon. Facebook Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR & VR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, firmware, and algorithms.We are growing our ASIC Design and Architecture team within FRL and are seeking engineers at all levels who will work with a world-class group of researchers and engineers to implement and contribute to the development and optimization of low power machine learning accelerators and state-of-the-art SoCs.
- Contribute to the development of efficient Architectures and contribute to ASIC digital Architecture, design and verification.
- Understand our in-house IPs needed and how they need to be integrated, connected and verified.
- Drive the top-level Architecture definition and develop the necessary RTL.
- Drive the chip-level integration, verification plan development and verification.
- Support the test program development, chip validation and chip life until production maturity.
- 4+ years of experience as a Digital Design Engineer and/or a Chip Lead.
- Experience in RTL coding, synthesis and/or SoC Integration.
- Experience in digital design Architecture.
- BS Electrical Engineering/Computer Science or equivalent experience.
- Python (or similar) scripting experience.
- Experience in SoC integration and ASIC architecture.
- Experience with Machine learning, graphics or computer vision accelerators.
- SystemVerilog OVM/UVM experience.