Sr Principal ASIC Design Engineer (NetSec)

Your CareerJoin our ASIC team and help deliver the digital logic that powers our next-generation firewall platforms. As a Senior Principal Engineer, you will take end-to-end ownership of complex modules or subsystems from architectural definition through silicon bring-up. You will provide technical leadership, collaborate extensively with world-class verification and physical design engineers to hit aggressive performance, power, and schedule goals, and mentor less experienced team members. This role requires a deep technical background in ASIC design for networking applications and the ability to independently drive major design efforts.Your ImpactDefine and document clear, comprehensive design and micro-architecture specifications for complex digital logic blocks and subsystemsDesign high-quality, high-performance SystemVerilog RTL that meets aggressive area, performance, and power targets, with particular emphasis on complex datapath designsLead debug efforts across simulation, emulation, formal methods, and silicon bring-up environments.Partner closely with verification engineers to define test plans, debug complex scenarios, close coverage, and add design-for-debug featuresCollaborate effectively with physical design teams, including reviewing synthesis/timing reports, rewriting RTL to close critical paths, analyzing timing, power, and area reports, and consulting on floor-planning for congestion/routability. Drive timing closure from an RTL perspective, understanding core concepts like setup/hold constraints and delay sourcesMentor junior and senior staff engineers, providing technical guidance and fostering their growth in ASIC design best practices, particularly in areas like design methodology and problem-solving approach