Vacancy caducado!
Job Description
Role: Design Engineer-Verilog/AI/Data CacheLocation: Santa Clara, CAEmp Type: Full Time JobInterview: Phone/Skype
What you'll doing:Working on state of the art data cache architecture serving high performance AI processing elements.
Skills needed:We are looking for 2 to 4 years of experience in the following areas (will consider bright candidates with lower experience)A) Understanding of cache pipeline design and microarchitectureB) Logic design experience with state of the art deep submicron technologies specifically low power design techniquesC) Strong understanding of processor and computer architectureD) Verilog / system Verilog / Synthesis / STA (Stating timing analysis) / CDC / LINTE) Knowledge of programming languages C, scripting (Perl / shell / python / awk) is a plus
Additional Information
All your information will be kept confidential according to EEO guidelines.
Vacancy caducado!