Vacancy caducado!
Title: Verification EngineerLocations: San Jose, CA Duration: 12 months (possibilities for extension)Responsibilities:
- Verification of complex Processor based IP/Sub-system and/or ASIC datapath at top-level
- Environment development (UVM), test plan development and execution, coverage closure, and reviews
- 8+ years’ experience in ASIC/FPGA verification, including verification of complex ASICs at chip-level
- Expertise in SystemVerilog and UVM based environment development
- Scripting/Perl/Python preferredHigh-Speed Networking protocol – Ethernet/PCIe/TCP-IP/AXI/DDR Preffered
- OR at least three SoC or IP Verification projects and hands on experience of developing assertion, checkers, coverage and scenario creation