Role: Mask Layout Design Engineer
Location: San Jose CA
Job Type: Contract
Interview: Phone/Skype
Key Responsibilities:
Design and implement custom memory hashtag#layouts for advanced technology nodes, collaborating with hashtag#circuitdesigners to optimize performance, power, and area.
Perform hashtag#physicalverification (LVS, DRC, ANT, etc.) and debug memory layout.
Mitigate layout design effects such as N-well proximity effect, diffusion spacing effect, and length of diffusion effects.
Collaborate with SoC partners to develop cutting-edge hashtag#SRAM and Register File layout designs.
Participate in design reviews to improve the quality of memory layouts.
Stay updated with the latest industry trends and developments in memory layout design.
Lead and mentor junior layout engineers and provide guidance on layout techniques.
Adhere to project timelines to ensure deliverables are met according to project schedules.
Communicate effectively with the design team to clarify and realize the layout requirements based on the schematic design intent.
Must be able to switch between manufacturing nodes with minimal ramp-up.
Qualifications:
7+ years of experience in analog/mixed-signal layout design of deep submicron hashtag#CMOS circuits, including at least 3+ years of recent experience on advanced nodes, such as hashtag#FinFET technologies.
Great understanding of hashtag#CAD flows and tools related to analog/mixed-signal layout design.
Excellent programming skills in languages: hashtag#SKILL, hashtag#Perl; hashtag#Python is a plus.
Strong fundamentals in software development.
Solid experience with hashtag#EMIR (RV), Physical design verification (hashtag#DRC / hashtag#LVS / hashtag#PEX / hashtag#ERC), waiver.
Working knowledge of hashtag#circuitdesign concepts such as device characteristics, SPICE and Verilog netlists, and simulation.
Excellent communication and interpersonal skills.
Preferred Tools:
Cadence hashtag#Virtuoso (Priority: 1)
Mentor hashtag#Calibre (Priority: 1)
Python (Priority: 2)