Design Verification Engineer : 2020-10-31

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Title; Design Verification Engineer

Location: Menlo Park CA

Type: Full time role Experience Range5 -7 YearsJob Description & Skill RequirementWhat are the top 3 "must have non-negotiable" skill sets that need to be present on a resume?System Verilog, UVM, Experience with writing testbench and testcasesPreferable - DSP/GPU block/top level verification experience, OCP/AMBA protocol experienceProcessor based block/Subsystem or SoC verification using C/CAre there any specific certifications, educational background or portfolios that you’re looking for?No BE or ME EE/CE/CS would be ok.Are you open to candidates who can only work remote?Ok during COVID19 outbreak but prefer onsite working at FB office with us.

RESPONSIBILITIESWrite and augment existing testplans.Implement testbench and scoreboards / checkers.Implement test sequences as per plan and debug failuresAchieve 100% functional and code coverageWork closely with designers, micro architects & f/w to resolve issuesAbility to communicate & articulate clearly progress / issues with project leads

Skills: MINIMUM QUALIFICATIONS5+ years of proven experience as a DV engineerHands on experience with SV and UVMHands on Experience with executable test plans and Coverage Driven verificationHands on Experience with Synopsys VCS / Verdi or Cadence Incisive toolsFamiliarity with C/C

PREFFERED QUALIFICATIONSPython (or similar) scripting languageASIC design experienceExperience in DSP based Audio or Computer Graphics or Compression' is desirable

Education: Bachelor's degree Required Skills:ARTICULATE, ENGINEER, TEST PLANS, APPLICATION-SPECIFIC INTEGRATED CIRCUIT, ASICAdditional Skills:ASIC DESIGN, C, CADENCE, DEBUG, PYTHON, SCRIPTING, SYNOPSYS Thanks & RegardsHardeep KambojSenior Technical RecruiterRADIANSYS INCDeskEXT 1003Text: 408-766-2197Email :- 39510 Paseo Padre Pkwy, Suite 110 Fremont. CA 94538

ID	#5358991
Estado	California
Ciudad	Menlopark
Tipo de trabajo	Permanent
Salario	Depends on Experience
Fuente	Radiansys, Inc.
Showed	2020-10-31
Fecha	2020-10-30
Fecha tope	2020-12-28
Categoría	Art/media/diseño
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Job Details

Design Verification Engineer