Design Verification - Verilog/systemVerilog coding

California, Burlingame

Vacancy caducado!

Job Description: DescriptionWhat are the top non-negotiable skill sets required for this role?• Experience in RTL design• Experience in micro-Architecture• Familiarity with Verilog/systemVerilog coding• Familiarity with design verificationDuties:• Contribute to the development of efficient micro-Architectures and contribute to ASIC digital micro-Architecture, design and verification• IP integration• Understand Design for Verification concepts• Contribute to top-level micro-Architecture definition and the necessary RTL development• Contribute to the chip-level integration, verification plan development and verification• Support the test program development, chip validation and chip life until production maturity• Contribute to frontend implementation such as synthesis for design analysisSkills Must Have:• 5+ years of experience as a RTL Design Engineer• Experience in micro-architecture, RTL coding, synthesis and/or SoC Integration• System Verilog OVM/UVM experience• Experience in SoC integration and ASIC architecture• Experience in designs like ISP/DSP• Tcl and Python (or similar) scripting experienceWish List/ Nice to Have:• FPGA design • Experience in CPU/GPU design• Experience in machine learning related designEducation:• Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science• Master's Degree preferred but not requiredComments for Suppliers:

Suscribir Reportar trabajo