ASIC Design Verification Engineer at Phoenix

ASIC Design Verification Engg Phoenix, AZ 12+ Months (Possible Hire after 3 to 6 months) Standard SV/UVM skills. If they have experience working on SERDES IP's and Server side silicon projects, that's a huge bonus. 4-7yrs of exp. CL8 We re looking for SoC Design Verification Eng. to provide design verification services for multi CPU/DSP SoC RESP: Testbench devel. - System Verilog UVM and C tests Integration/devel. of C tests/APIs and SW build flow, UVM mailboxes and HW/SW communication components Integr. of lower level UVM testbenches Test plan devel. Power Aware testbench devel. and simulations Seamless porting between simulation/emulation/prototyping platforms Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto Coverage collection and closure Working w/ cross functional teams (DV/Arch/Design/FW) to identify coverage scope MIN QUAL: 5+ yrs of exp. in RTL Design and Verification area of which 2+ yrs of exp. in SoC Design Verification and HW/SW verif. Deep knwl. of System Verilog UVM and vertical testbench integration Knwl of low level HW/SW interaction and debug and multi CPU and debug arch. Exp. w/ devel. of fully automated flows Please contact hjoshi at everythingd dot com for more details