Vacancy caducado!
Location: Cambridge, MA Description: The Judge Group has an opportunity for a Principal Digital ASIC Designer. You will be responsible for implementing designs from RTL through synthesis, scan insertion, timing closure, implementation and layout. Looking for candidates with solid skills in back-end digital systems design with experience in design flows from Cadence or Synopsys, and a working knowledge of analog design principles and signal / power integrity. Familiarity with architectures for secure systems design, e.g., cryptographic encoders / decoders or tagged processor architectures is a plus. Demonstrated experience with successful tapeouts at advanced nodes is required. Experience leading and managing design teams is also required. Will be required to obtain and maintain a U.S. Security Clearance. PhD+10 or MSEE+15 years experience preferred
Requirements: Fluent in Verilog/VHDL Fluent in Cadence or equivalent Digital ASIC Tool Suite, e.g., Genus, Innovus, Tempus, Voltus, etc. Experience with high-level design, simulation, and verification tools Experience with scripting languages Python/PERL and regular expressions Familiarity with analog ASICs: Voltage and Current sources, Amplifiers, Converters, PLLs, and Transceivers Contact: This job and many more are available through The Judge Group. Find us on the web at www.judge.comVacancy caducado!