Vacancy caducado!
- Prior experience in timing and or RTL design of high-speed interfaces.
- Prior experience of collaborating with Physical Design teams in multiple successful ASIC/IP tapeouts.
- Knowledge of the IP/SoC level timing closure flow and methodology.
- Experience in IP/ASIC timing constraints generation. Expertise in STA tools and flow
- Hands on experience in timing constraints generation and management
- Proficiency in scripting languages (TCL and Perl)
- Familiarity with synthesis, logic equivalence, DFT and backend related methodology and tools
- Capability to understand and implement improvements to existing methodologies and flows.
- Strong background in Constraint analysis and debug, using industry standard tools.
- Good understanding and experience in timing closure of various test modes such as scan shift, scan capture, atspeed and BIST testing.
- Team player with a passion to innovate and can-do attitude.
- Self-starter and highly motivated.
- Knowledge of DDR/GDDR DRAM protocol; high-speed PHYs
- Experience designing or integrating IP
- Experience in high speed and low power digital design using advanced deep micron process.
- Experience with highly configurable designs
Vacancy caducado!